AT87251G2D-3CSUM【PDF 18/77 页】IC 8051 MCU 32K OTP 24MHZ 40DIP

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AT/TSC8x251G2D

4135F–8051–11/06

4. If this instruction addresses external memory location, add 2(N+2) to the number of

states (N: number of wait states).

Table 21.

Summary of Increment and Decrement Instructions

Notes: 1. A shaded cell denotes an instruction in the C51 Architecture.

2. If this instruction addresses an I/O Port (Px, x = 0-3), add 2 to the number of states.

Add 3 if it addresses a Peripheral SFR.

IncrementINC <dest>dest opnd

← dest opnd + 1

IncrementINC <dest>, <src>dest opnd

← dest opnd + src opnd

DecrementDEC <dest>dest opnd

← dest opnd - 1

DecrementDEC <dest>, <src>dest opnd

← dest opnd - src opnd

Mnemonic

<dest>,

<src>

(1)

Comments

Binary Mode

Source Mode

Bytes

States

Bytes

States

INC

DEC

AACC by 1

dir8

Direct address (on-chip RAM or

SFR) by 1

22(2)

at Ri

Indirect address by 1

INC

DEC

Rm, #short

Byte register by 1, 2, or 4

WRj, #short

Word register by 1, 2, or 4

INC

DRk, #short

Double word register by 1, 2, or 4

DEC

DRk, #short

Double word register by 1, 2, or 4

INC

DPTR

Data pointer by 1

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